The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 2006
Filed:
Nov. 13, 2001
Wen-yen Hwang, Sugar Land, TX (US);
Klaus Alexander Anselm, Sugar Land, TX (US);
Wen-Yen Hwang, Sugar Land, TX (US);
Klaus Alexander Anselm, Sugar Land, TX (US);
Applied Optoelectronics, Inc., Sugar Land, TX (US);
Abstract
Methods for fabricating a VCSEL having current confinement, the VCSEL having a substrate, a semiconductor active region, and a bottom mirror disposed between the substrate and the active region. A first top spacer layer is epitaxially grown on the active region, the first top spacer layer comprising a current-spreading buffer layer disposed on the active region, a current-confinement layer disposed on the buffer layer, and a current-spreading platform layer disposed on the current-confinement layer, wherein the combined thickness of the platform and current-confinement layers is less than the thickness of the buffer layer. A current-confinement structure having an annular region of enhanced resistivity and a central aperture of comparatively lower resistivity is formed in the current-confinement layer using ion implantation. Subsequently, epitaxial regrowth is performed to form a second top spacer layer on the platform layer, said second top spacer layer comprising a top current-spreading layer. The resulting current-confinement structure is the result of a shallower ion implantation and thus has more precise dimensions and can be closer to the active region.