The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2006

Filed:

Oct. 25, 2002
Applicant:

B. Arlen Young, Palo Alto, CA (US);

Inventor:

B. Arlen Young, Palo Alto, CA (US);

Assignee:

Adaptec, Inc., Milpitas, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A host adapter, which interfaces two I/O buses, caches data transferred from one I/O bus to another I/O bus in a data first-in-first-out (FIFO)/caching memory. In addition, when a target device on the another I/O bus is ready to receive the data, data is transferred from the data FIFO/caching memory even though not all of the data may be cached in that memory. Hence, data is concurrently transferred to and transferred from the data FIFO/caching memory. The data transfer to the target device is throttled if cached data is unavailable in the data FIFO/caching memory for transfer, e.g., the data cache is empty for the current context.


Find Patent Forward Citations

Young, B.. (2006). Host adapter integrated data fifo and data cache and method for improved host adapter sourcing latency (U.S. Patent No. 7024523). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7024523

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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