The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2006

Filed:

Jan. 24, 2002
Applicants:

Douglas Markham Washabaugh, Hubbardston, MA (US);

Thomas Anderson, Hudson, NH (US);

Kathryn Fuller, North Reading, MA (US);

Inventors:

Douglas Markham Washabaugh, Hubbardston, MA (US);

Thomas Anderson, Hudson, NH (US);

Kathryn Fuller, North Reading, MA (US);

Assignee:

Riverstone Networks, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/56 (2006.01);
U.S. Cl.
CPC ...
Abstract

Different levels of service are provided to different types of traffic within a single virtual circuit (VC) by converting the traffic from fixed-length cells to variable-length packets, classifying the packets based on information in the packet headers, associating the packets with a VC, and then implementing class-specific enqueuing and dequeuing of the classified packets on a per-VC basis. Classified packets are dequeued from VC-specific and class-specific queues into VC-specific segmentation and re-assembly (SAR) queues according to an algorithm that is a function of traffic class. The dequeuing algorithm determines the level of service that is provided to the different classes of traffic within each VC. Packets are dequeued from the VC-specific SAR queues and converted back to fixed-length cells according to an algorithm that arbitrates among multiple VC-specific SAR queues. The technique for managing traffic can be carried out within an Ethernet switch/router that includes input and output ATM interfaces.


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