The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2006
Filed:
Jan. 28, 2002
Prasad N. Golla, Plano, TX (US);
Gerard Damm, Dallas, TX (US);
John Blanton, Dallas, TX (US);
Mei Yang, Richardson, TX (US);
Dominique Verchere, Plano, TX (US);
Hakki Candan Cankaya, Dallas, TX (US);
Yijun Xiong, Plano, TX (US);
Prasad N. Golla, Plano, TX (US);
Gerard Damm, Dallas, TX (US);
John Blanton, Dallas, TX (US);
Mei Yang, Richardson, TX (US);
Dominique Verchere, Plano, TX (US);
Hakki Candan Cankaya, Dallas, TX (US);
Yijun Xiong, Plano, TX (US);
Alcatel, Paris, FR;
Abstract
A scheduling system and methodology for use in a network switch element having multiserver, multiple-arbiter architecture. Ingress ports and egress ports coupled to the cross-connect fabric of the network element are provided with multiple ingress and egress arbiters, respectively, for effectuating an iterative arbitration strategy such as RGA or RG. Arbiter architectures include singe-arbiter-per-port; single-arbiter-per-server; multiple-arbiters-per-port; and multiple-arbiters-per-server arrangements, wherein the arbiters can be implemented using RRA, BTA, Flexible Ring, or any other arbiter technology. Depending on the iteration strategy, ingress arbiter architecture and egress arbiter architecture, a variety of iterative, multiserver-capable scheduling algorithms can be obtained, which scheduling algorithms can also be implemented in QoS-aware network nodes.