The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2006
Filed:
Apr. 17, 2003
Kazuaki Sogawa, Katano, JP;
Ryoichi Suzuki, Takatsuki, JP;
Kazuaki Sogawa, Katano, JP;
Ryoichi Suzuki, Takatsuki, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
In a dual loop PLL having a frequency comparison loop and a phase comparison loop, when an input control circuitof an up/down counterreceives an UP signal from a frequency comparator, the input control circuitoutputs a positive value of a ½ of a previous addition/subtraction result value. When the input control circuitreceives a DOWN signal from the frequency comparator, the input control circuitoutputs a negative value of a ½ of the previous addition/subtraction result value. A registerstores a count value. The adderadds the output of the input control circuitto the output of the register. Thus, the up/down counterincrements or decrements by a ½ value of the previous addition/subtraction result value, and the dual loop PLL performs a frequency comparison based on a dichotomizing search method. Therefore, even when the output frequency is high, the frequency comparison is efficiently performed, and the lock up time is reduced.