The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2006
Filed:
Aug. 27, 2004
Jochen Thomas, Munich, DE;
Juergen Grafe, Dresden, DE;
Ingo Wennemuth, Munich, DE;
Minka Gospodinova-daltcheva, Munich, DE;
Maksim Kuzmenka, Munich, DE;
Jochen Thomas, Munich, DE;
Juergen Grafe, Dresden, DE;
Ingo Wennemuth, Munich, DE;
Minka Gospodinova-Daltcheva, Munich, DE;
Maksim Kuzmenka, Munich, DE;
Infineon Technologies AG, Munich, DE;
Abstract
The invention relates to an FBGA arrangement, comprising a substrate on which at least one chip is chip-bonded face-down, which has a central row of bonding pads connected to contact islands (landing pads) on the substrate by a bonding channel in the substrate via wire bridges, which substrate, for its part, is provided with soldering balls—arranged in an array—for contact connection to a printed circuit board, and the contact islands and the soldering balls being connected to one another via a rewiring of the substrate. The preferred embodiment of the invention is intended to provide an FBGA arrangement which supports the center pad row technology and at the same time has low electrical parasitics. This is achieved by virtue of the fact that at least two substrates () are provided, the substrates () are provided substratewise in each case with bonding channels () having different dimensions, in a manner forming a multistage bonding channel, the bonding channels () in the ball-side substrate () having larger dimensions than those in the chip-side substrate ().