The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2006

Filed:

Oct. 11, 2002
Applicants:

Yutaka Kaneda, Kanuma, JP;

Keiichi Naito, Kanuma, JP;

Soichiro Kishimoto, Kanuma, JP;

Toshihiro Shinohara, Kanuma, JP;

Inventors:

Yutaka Kaneda, Kanuma, JP;

Keiichi Naito, Kanuma, JP;

Soichiro Kishimoto, Kanuma, JP;

Toshihiro Shinohara, Kanuma, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01K 3/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

An object of the present invention is to manufacture a bump-attached wiring circuit board with which stable bump connections are possible, and there is no need for bothersome operations such as plating pretreatments. A bump formation etching mask () is formed on the bump formation side () of a metal foil () having a thickness (t+t) equal to the sum of the thickness tof a wiring circuit () and the height tof the bumps () to be formed on a wiring circuit (), the bumps () are formed by half-etching the metal foil () from the bump formation etching mask () side down to a depth corresponding to a predetermined bump height tand a metal thin film layer () composed of a different metal from the metal foil () is formed on the bump formation side of the metal foil (), thereby providing a bump-attached wiring circuit board with which stable bump connections are possible, and there is no need for bothersome operations such as plating pretreatments.


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