The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2006
Filed:
Jul. 02, 2004
Automated processor generation system for designing a configurable processor and method for the same
Earl A. Killian, Los Altos Hills, CA (US);
Ricardo E. Gonzalez, Menlo Park, CA (US);
Ashish B. Dixit, Mountain View, CA (US);
Monica Lam, Menlo Park, CA (US);
Walter D. Lichtenstein, Belmont, MA (US);
Christopher Rowen, Santa Cruz, CA (US);
John C. Ruttenberg, Newton, MA (US);
Robert P. Wilson, Palo Alto, CA (US);
Albert Ren-rui Wang, Fremont, CA (US);
Dror Eliezer Maydan, Palo Alto, CA (US);
Earl A. Killian, Los Altos Hills, CA (US);
Ricardo E. Gonzalez, Menlo Park, CA (US);
Ashish B. Dixit, Mountain View, CA (US);
Monica Lam, Menlo Park, CA (US);
Walter D. Lichtenstein, Belmont, MA (US);
Christopher Rowen, Santa Cruz, CA (US);
John C. Ruttenberg, Newton, MA (US);
Robert P. Wilson, Palo Alto, CA (US);
Albert Ren-Rui Wang, Fremont, CA (US);
Dror Eliezer Maydan, Palo Alto, CA (US);
Tensilica, Inc., Santa Clara, CA (US);
Abstract
An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.