Apparatus and method for snoop access in a dual access, banked and pipelined data cache memory unit

Abstract

In a data cache unit that exchanges data signal groups with at least two execution units, the operation of the data cache unit is implemented as a three-stage pipeline in order to access data at the speed of the system clock. The data cache unit has a plurality of storage cell banks. Each storage cell bank has valid bit array unit and a tag unit for each execution unit incorporated therein. Each valid bit array unit has a valid/invalid storage cell associated with each data group stored in the storage cell bank. The valid bit array units have a read/write address port and snoop address port. During a read operation, the associated valid/invalid signal is retrieved to determine whether the data signal group should be processed by the associated execution unit. In a write operation, a valid bit is set in the valid/invalid bit location(s) associated with the storage of a data signal group (or groups) during memory access. The valid bit array unit responds to a snoop address and a control signal from the tag unit to set an invalid bit in a valid/invalid bit address location associated with the snoop address. The tag unit can be divided into a plurality of tag subunits to expedite processing.