The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2006

Filed:

Dec. 16, 2003
Applicant:

Daniel J. Ferris, Lakeville, MN (US);

Inventor:

Daniel J. Ferris, Lakeville, MN (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/22 (2006.01);
U.S. Cl.
CPC ...
Abstract

According to one embodiment, a locally regulated circuit regulates current flows (Iand I) through the operation of a current mirror (). The regulated current flows are used to self-generate a common mode voltage (V) at node () and to produce the required bias signals through input stage (and) and output stage (and) in response to data input signals (D and D-complement). Cancellation of common mode voltage variation is further enhanced by generating a supplemental current in response to an error signal generated by comparing a desired common mode voltage (V) to the actual common mode voltage at node (). The supplemental current conducted by either of loads (and) serves to regulate the common mode voltage at node ().


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