The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2006
Filed:
Dec. 20, 2004
Terrence Harold Brown, Harwood, MD (US);
Larry Gene Ferguson, Baltimore, MD (US);
Terrence Harold Brown, Harwood, MD (US);
Larry Gene Ferguson, Baltimore, MD (US);
The United States of America as represented by the National Security Agency,, Washington, DC (US);
Abstract
The present invention is a method of surface preparation and imaging for integrated circuits. First, a substrate is selected and an opening is cut in the substrate of a sufficient size to fit an integrated circuit to be analyzed. A second substrate is then selected. An adhesive film is applied to the top surface of the first substrate, the adhesive film having adhesive on both sides and covering the opening on the first substrate. An integrated circuit is then inserted into the opening and attached to the bottom side of the adhesive film. Next, the first substrate and integrated circuit are bonded to the second substrate using the adhesive film. The bottom side of the first substrate and the integrated circuit are then thinned until the substrate wafer of the integrated circuit is completely removed. The bottom side of the first substrate and integrated circuit is then thinned to a user-definable level. A handle wafer is then attached to the bottom side of the first substrate. The second substrate is then removed and thinned and an analytical imaging technique is performed on the integrated circuit from the top side of the first substrate. The first substrate and integrated circuit are optionally repeatedly destructively processed to a user-definable level. Processing and imaging steps are repeated as desired on this user-definable level preferably down to just one level.