The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2006
Filed:
Mar. 22, 2004
Manabu Iguchi, Kanagawa, JP;
Akira Matumoto, Kanagawa, JP;
Masahiro Komuro, Kanagawa, JP;
NEC Electronics Corporation, Kanagawa, JP;
Abstract
A semiconductor device having a multilayer interconnection structure includes a chip semiconductor substrate, a plurality of interlayer insulating layers disposed on the chip semiconductor substrate, a circuit section disposed on the chip semiconductor substrate, and a plurality of walls that extend through the interlayer insulating layers and are arranged along the peripheral portions of the chip semiconductor substrate such that the walls surround the circuit section. The walls include upper sub-walls and lower sub-walls. The upper sub-walls extend through one of the interlayer insulating layers and further extend into another one of the interlayer insulating layers disposed under the layer through which the upper sub-walls extend. The lower sub-walls extend through one of the interlayer insulating layers disposed under the layer through which the upper sub-walls extend. Lower portions of the upper sub-walls each extend into corresponding upper portions of the lower sub-walls.