The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2006

Filed:

Sep. 28, 2004
Applicants:

William Wong, San Carlos, CA (US);

Chinwen Shih, Santa Clara, CA (US);

Rene A. Lujan, Sunnyvale, CA (US);

Eugene Chow, Mountain View, CA (US);

Inventors:

William Wong, San Carlos, CA (US);

Chinwen Shih, Santa Clara, CA (US);

Rene A. Lujan, Sunnyvale, CA (US);

Eugene Chow, Mountain View, CA (US);

Assignee:

Palo Alto Research Center, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/77 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
Abstract

Various exemplary embodiments of the systems and methods according to this invention provide for a method of producing a self-aligned thin film transistor, the transistor including a metal layer covering at least a portion of a doped layer, the doped layer covering at least a portion of a dielectric layer, a strain being created in the metal layer, the method includes etching an exposed portion of the doped layer to create a defect at an interface between the doped layer and the dielectric layer so as to initiate a delamination of the doped layer from the dielectric layer. The delamination of the doped layer from the dielectric layer is stopped when the defect propagates into an interface between the doped layer and the dielectric layer that has an adhesive energy that is greater than the strain of the metal layer.


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