Performance built-in self test system for a device and a method of use

Abstract

A semiconductor device is disclosed that include a built-in self test system. The device comprises a logic function and a self test engine coupled and integrated with the logic device. The device includes a performance code storage coupled and integrated with the logic function. The performance code storage contains at least one critical path pattern that will be run on the logic function to determine the performance of the logic function when the self test engine causes the logic function to be in a performance test mode. In summary, a performance sort/validate integrated custom logic device, like a microprocessor core can be tested without the need for a separate, high-performance tester. A performance built-in self test (PBIST) approach provides a basic test procedure to be utilized within the device. An integrated memory array, such as the L1-cache, is provided wherein a select set of SRAM memory words are preconditioned at the time of manufacture to contain predefined functional patterns.