The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7016244 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 21, 2006

Filed:

May. 12, 2004
Applicants:

Stefan Sommer, Fuerth, DE;

Wolfgang Spirkl, Germering, DE;

Inventors:

Stefan Sommer, Fuerth, DE;

Wolfgang Spirkl, Germering, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

For testing or for characterizing output drivers of output circuits of high-speed semiconductor memory devices under conditions close to an application, scan elements are provided at the inputs of the output circuits. The scan elements in each case have a register function and are cascaded to form a scan chain. Via the scan chain, test data signals are applied to the inputs of the output circuits whilst bypassing a memory cell array of the semiconductor memory devices. The characterization of data signals of the high-speed semiconductor memory devices that are output by the output circuits requires only a test memory controller not connected to the data signal terminals and a passive load simulation of the application memory controller.


Find Patent Forward Citations

Sommer, Stefan. (2006). Method and arrangement for testing output circuits of high speed semiconductor memory devices (U.S. Patent No. 7016244). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7016244

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