Power-on reset circuit with low standby current and self-adaptive reset pulse width

Abstract

A power-on reset circuit for an integrated circuit includes a voltage threshold detector circuit for generating a first signal, a DC biasing start-up circuit providing start-up currents and a first control signal, a self-regulating watchdog current source providing bias currents and a counter circuit for counting a predetermined number of cycles when enabled by the first control signal and providing a second control signal when the count is completed. The POR circuit asserts the reset signal when the first signal is asserted and deasserts the reset signal when both the first signal and the second control signal are deasserted. The POR circuit merges accurate detection of the full range of Vdd events with a self-adapting current source. In addition, the POR circuit employs 'pulse-stretching' techniques operating independently but mutually working together to create a POR assertion persistence in the time domain that further enhances the reliability of POR signal effectiveness.