The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2006

Filed:

Jan. 24, 2001
Applicants:

Bassel Beidas, Alexandria, VA (US);

Olga Ritterbush, Rockville, MD (US);

Stanley Kay, Rockville, MD (US);

Yezdi Antia, Gaithersburg, MD (US);

Bala Subramaniam, Potomac, MD (US);

Inventors:

Bassel Beidas, Alexandria, VA (US);

Olga Ritterbush, Rockville, MD (US);

Stanley Kay, Rockville, MD (US);

Yezdi Antia, Gaithersburg, MD (US);

Bala Subramaniam, Potomac, MD (US);

Assignee:

Hughes Electronics Corporation, El Segundo, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04J 3/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and system for tracking a time division multiplexed synchronization signal in a satellite communication system is provided. The signal is provided as a series of frames with beacon signals time division multiplexed into at least one time slot of each frame. The beacon signal in each frame comprises a unique word sequence, which is the same in each frame, and a portion of a PN sequence. The entire PN sequence is distributed into a plurality of frames forming a superframe. Frequency variations of the incoming signal are tracked at the satellite terminal by correlating the PN sequence of the incoming signal against early and late locally generated versions of the PN sequence in a discriminate circuit. The output of the discriminate is provided to a delay locked loop circuit of at least third order. The output of the loop is used to adjust the frequency of the VCO, which clocks the A/D converter operating on the incoming signal. The product of the PN sequence of the incoming signal and an on-time locally generated version of the PN sequence is provided to an FFT circuit. The satellite terminal determines if it is locked onto the incoming signal based on the output of the FFT. If the satellite terminal is not locked, the terminal returns to an acquisition mode.


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