The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 14, 2006
Filed:
Sep. 12, 2002
Tadayoshi Nakatsuka, Toyonaka, JP;
Toshiharu Tambo, Kyoto, JP;
Takahiro Kitazawa, Uozu, JP;
Akiyoshi Tamura, Suita, JP;
Katsuyoshi Tara, Kyoto, JP;
Tadayoshi Nakatsuka, Toyonaka, JP;
Toshiharu Tambo, Kyoto, JP;
Takahiro Kitazawa, Uozu, JP;
Akiyoshi Tamura, Suita, JP;
Katsuyoshi Tara, Kyoto, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
A semiconductor device whose insertion loss is reduced and isolation characteristics are improved in a high frequency band by reducing the capacitance component when an FET is off is provided. FETs () having a gate electrode with a gate length of not more than 0.8 μm are formed on a semiconductor substrate in which a buffer layer () having an impurity concentration of at least 10cmand at most 10cmis formed on a semi-insulating semiconductor () having at least 10cmand at most 10cmp-type or n-type impurities and an active layer () having a p-type or n-type impurity concentration of at least 10cmand at most 10cmis formed on the buffer layer. N FETs are combined with each other, and when 1≦m≦n−1 (n and m are integers, n>1), a drain terminal of an m-th FET is connected to a source terminal of an (m+1)th FET, resistors () are connected to the gate electrodes of all of the first to n-th FETs, and all of the other ends of the resistors are coupled to the same electric potential.