The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 2006
Filed:
Aug. 28, 2001
Method and apparatus for generating superset pinout for devices with high-speed transceiver channels
Applicant:
James H. Lie, Santa Clara, CA (US);
Inventor:
James H. Lie, Santa Clara, CA (US);
Assignee:
Cypress Semiconductor Corp., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 7/38 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method for generating a superset pinout for a family of devices. First, a pinlist is defined for each device within the family of devices. Second, a superset listing of pins is generated from the pinlist. Third, the superset pinout for the family of devices is created from said superset listing of pins to eliminate potential footprint variations within the family of devices. Fourth, each pin of the superset pinout associated with each member of the family of devices is marked.