The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 2006
Filed:
Oct. 09, 2002
Robert W. Bassett, Essex Junction, VT (US);
Garrett S Christensen, Endicott, NY (US);
Michael L. Combs, Essex Junction, VT (US);
L. Owen Farnsworth, Lincoln, VT (US);
Pamela S. Gillis, Jericho, NY (US);
Robert W. Bassett, Essex Junction, VT (US);
Garrett S Christensen, Endicott, NY (US);
Michael L. Combs, Essex Junction, VT (US);
L. Owen Farnsworth, Lincoln, VT (US);
Pamela S. Gillis, Jericho, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for reducing Pin Count Test design and test that allows parametric test patterns for high pin count ASICs to be applied using low pin count testers. The same boundary scan structure used to isolate the test of internal logic to a small number of test I/O is also used to apply parametric external I/O tests to the ASIC's functional I/O. The parametric tests are banked into pin groups and applied on the same low pin count tester used for the internal logic tests.