The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 2006
Filed:
Dec. 09, 2002
Tsutomu Hoshino, Iwatsuki, JP;
Hiroshi Sugita, Iwatsuki, JP;
Kenichi Sonobe, Iwatsuki, JP;
Hirota Takahashi, Iwatsuki, JP;
Kazuya Edogawa, Iwatsuki, JP;
Tomokazu Kaneko, Iwatsuki, JP;
Tsutomu Hoshino, Iwatsuki, JP;
Hiroshi Sugita, Iwatsuki, JP;
Kenichi Sonobe, Iwatsuki, JP;
Hirota Takahashi, Iwatsuki, JP;
Kazuya Edogawa, Iwatsuki, JP;
Tomokazu Kaneko, Iwatsuki, JP;
Fuji Xerox Co., Ltd., Tokyo, JP;
Abstract
In a CPU, a FET is turned off and power is not supplied to a power supply element of a transceiver for a period of time until predetermined initialization processing, which is implemented in a peripheral device when power is supplied via a cable from a host PC, has been concluded (i.e., a period of time until it becomes possible for the peripheral device to initiate data communication with the host PC). Thus, even if the peripheral device and the host PC are physically connected by a cable, data signals transmitted along signal lines are not relayed by the transceiver to a logic controller, whereby it in effect becomes possible to set the peripheral device in a pseudo-non-connected state with respect to the host PC.