The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2006

Filed:

Aug. 27, 2003
Applicants:

Shiro Dosho, Ikeda, JP;

Yusuke Tokunaga, Ibaraki, JP;

Yasuyuki Doi, Nagaokakyo, JP;

Hirofumi Nakagawa, Kyoto, JP;

Yoshito Date, Otsu, JP;

Tetsuro Ohmori, Hirakata, JP;

Kaori Nishikawa, Osaka, JP;

Inventors:

Shiro Dosho, Ikeda, JP;

Yusuke Tokunaga, Ibaraki, JP;

Yasuyuki Doi, Nagaokakyo, JP;

Hirofumi Nakagawa, Kyoto, JP;

Yoshito Date, Otsu, JP;

Tetsuro Ohmori, Hirakata, JP;

Kaori Nishikawa, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

In the process of transferring a clock signal and a plurality of data signals which are in synchronization with the clock signal, a driving pulse width of a driver switch is feedback-controlled by a clock transmission system (), whereby the clock signal is transmitted at a small amplitude. A control signal having the pulse width is used for controlling the driver switch in each data transmission system (), whereby transfer of each data signal at a small amplitude is realized at the same time. Further, in a clock reception system (), the control signal having the pulse width is used in delay control of a clock delay circuit, whereby an optimum latch timing of received data in each data reception system () is realized.


Find Patent Forward Citations

Loading…