The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 2006
Filed:
Sep. 27, 2004
Applicants:
Daniel J. Pugh, San Jose, CA (US);
Andrew W. Fox, Pacific Grove, CA (US);
Dale Wong, San Francisco, CA (US);
Inventors:
Daniel J. Pugh, San Jose, CA (US);
Andrew W. Fox, Pacific Grove, CA (US);
Dale Wong, San Francisco, CA (US);
Assignee:
Agate Logic, Inc., Cupertino, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
A Field Programmable Gate Array (FPGA) core cell with one or more Look-Up Tables (LUTs) and a selectable logic gate is presented as a space-efficient alternative to the conventional LUT-based FPGA core cell. An algorithm based upon the familiar FlowMap algorithm for LUT-based FPGA core cells implements the mapping of a Boolean logic network into the disclosed FPGA core cell.