The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2006
Filed:
Sep. 08, 2003
Kiran K. Gullapalli, Austin, TX (US);
Mark M. Gourary, Moscow, RU;
Sergei G. Rusakov, Moscow, RU;
Sergei L. Ulyanov, Moscow, RU;
Mikhail M. Zharov, Moscow, RU;
Kiran K. Gullapalli, Austin, TX (US);
Mark M. Gourary, Moscow, RU;
Sergei G. Rusakov, Moscow, RU;
Sergei L. Ulyanov, Moscow, RU;
Mikhail M. Zharov, Moscow, RU;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A circuit on an integrated circuit is made from a design that is verified using a design tool. The design tool takes a model of the circuit and generates equations with respect to nodes on the circuit. The time consuming task of completely determining the voltage at each node is performed for a predetermined input. To determine the node voltages for other signals, the first order transfer function of the equations is taken and then calculated for the predetermined input. A first order estimate of the node voltages is achieved using this first order transfer function and the node voltages determined from the predetermined input. A second order estimate is achieved using the first order transfer function and the first order estimate. A third order estimate is achieved using the first order transfer function and the second order estimate. The circuit design is verified for manufacturabiltity then manufactured.