The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2006
Filed:
Mar. 26, 2004
Applicants:
Rajesh Manapat, San Jose, CA (US);
Ritesh Mastipuram, Santa Clara, CA (US);
Kannan Srinivasagam, Sunnyvale, CA (US);
Inventors:
Rajesh Manapat, San Jose, CA (US);
Ritesh Mastipuram, Santa Clara, CA (US);
Kannan Srinivasagam, Sunnyvale, CA (US);
Assignee:
Cypress Semiconductor Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
A memory device () can include memory cell arrays (-and-) accessed according to phase shifted clock signals. Memory cell array (-) can be accessed at double data rates essentially synchronous with clock signal CLK. Memory cell array (-) can be accessed at double data rates essentially synchronous with a phase delayed clock signal DCLK. Such an arrangement can provide eight data accesses (four reads and four writes) in a single clock cycle.