The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 2006
Filed:
Sep. 23, 2003
Chi-hui Lin, Taipei, TW;
Jeng-ping Lin, Taoyuan Hsien, TW;
Pei-ing Lee, Taipei Hsien, TW;
Jih-chang Lien, Taoyuan Hsien, TW;
Chi-Hui Lin, Taipei, TW;
Jeng-Ping Lin, Taoyuan Hsien, TW;
Pei-Ing Lee, Taipei Hsien, TW;
Jih-Chang Lien, Taoyuan Hsien, TW;
Nanya Technology Corporation, Taoyuan, TW;
Abstract
A split gate flash memory cell. The memory cell includes a substrate, a conductive line, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive line is disposed in a lower portion of the trench of the substrate. The source region is formed in the substrate adjacent to an upper portion of the conductive line having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate adjacent to the conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate adjacent to the first conductive layer.