The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2006

Filed:

Dec. 23, 2003
Applicants:

Woo Seok Cheong, Daejeon, KR;

Seong Jae Lee, Daejeon, KR;

Moon Gyu Jang, Daejeon, KR;

Inventors:

Woo Seok Cheong, Daejeon, KR;

Seong Jae Lee, Daejeon, KR;

Moon Gyu Jang, Daejeon, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A schottky barrier transistor and a method of manufacturing the same are provided. The method includes forming a gate insulating layer and a gate on a substrate, forming a spacer on a sidewall of the gate, and growing a polycrystalline silicon layer and a monocrystalline silicon layer on the gate and the substrate, respectively, using a selective silicon growth. A metal is deposited on the polycrystalline silicon layer and the monocrystalline silicon layer. Then, the metal reacts with silicon of the polycrystalline silicon layer and the monocyrstalline silicon layer to form a self-aligned metal silicide layer. Therefore, selective wet etching for removing an unreacted metal after silicidation can be omitted. Furthermore, etching damage caused during the formation of the spacer can be decreased during the growth of the monocrystalline silicon layer, thereby improving the electrical characteristics of devices.


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