The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2006

Filed:

Sep. 23, 2003
Applicants:

Shanjen Pan, Plano, TX (US);

James R. Todd, Plano, TX (US);

Sameer Pendharkar, Richardson, TX (US);

Tsutomu Kubota, Inbagun, JP;

Pinghai Hao, Plano, TX (US);

Inventors:

Shanjen Pan, Plano, TX (US);

James R. Todd, Plano, TX (US);

Sameer Pendharkar, Richardson, TX (US);

Tsutomu Kubota, Inbagun, JP;

Pinghai Hao, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

Depletion drain-extended MOS transistor devices and fabrication methods for making the same are provided, in which a compensated channel region is provided with p and n type dopants to facilitate depletion operation at Vgs=0, and an adjust region is implanted in the substrate proximate the channel side end of the thick gate dielectric structure for improved breakdown voltage rating. The compensated channel region is formed by overlapping implants for an n-well and a p-well, and the adjust region is formed using a Vt adjust implant with a mask exposing the adjust region.


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