The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2006
Filed:
Aug. 01, 2002
Thomas N. Valine, San Jose, CA (US);
Thomas N. Valine, San Jose, CA (US);
Sun Microsystems, Inc., Santa Clara, CA (US);
Abstract
A topology based approach to shielding wire generation for an integrated circuit design. The present invention generates various templates by sizing one or more signal wire geometries. The various templates are then geometrically added to and/or subtracted from to generate shielding wire patterns. In some embodiments, the templates may be merged to prevent duplicate shielding wire generation between adjacent signal wires that violates design rules. In some embodiments, the topology based approach permits shielding wire generation based upon complex signal wire geometries, such as branched signal wire geometries. The present invention can be implemented in CAD software and in CAD software together with a small amount of custom software to generate design rule clean (DRC) shielding wire generation that utilizes both power and ground nets.