The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2006

Filed:

Jun. 29, 2001
Applicants:

Debashis Bhattacharya, Plano, TX (US);

Vamsi Boppana, Santa Clara, CA (US);

Rajeev Murgai, Santa Clara, CA (US);

Rabindra Roy, Hillsboro, OR (US);

Inventors:

Debashis Bhattacharya, Plano, TX (US);

Vamsi Boppana, Santa Clara, CA (US);

Rajeev Murgai, Santa Clara, CA (US);

Rabindra Roy, Hillsboro, OR (US);

Assignee:

Zenasis Technologies, Inc., Campbell, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention pertains to an automated method for designing a integrated circuit (IC) design-specific cell, the method includes the steps of receiving a design specification for the design-specific cell, mapping a transistor-level representation of the design-specific cell, wherein the mapping is based on at least one, but perhaps plural design specifications, and evaluating the transistor-level representation of the design-specific cell for satisfaction of the design specification.


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