The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2006
Filed:
Jul. 17, 2001
Applicants:
Jean-marc Irazabal, Sunnyvale, CA (US);
Calto Wong, Sunnyvale, CA (US);
Inventors:
Jean-Marc Irazabal, Sunnyvale, CA (US);
Calto Wong, Sunnyvale, CA (US);
Assignee:
Koninklijke Philips Electronics N.V., Eindhoven, NL;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
Abstract
In an electronic device, a first electronic circuit is selectively operated in a selected one of at least two operating modes. A second electronic circuit is selectively operated in a power-up mode and a power-down mode. The second electronic circuit is put into the power-down mode if the first electronic circuit is operated in one of the at least two operating modes.
Quick Actions:
Irazabal, Jean-Marc. (2006). Power management method for setting clock circuit into power down mode if analog front end circuit is sampling input signals in an electronic device (U.S. Patent No. 7003682). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7003682
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile