The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2006
Filed:
Oct. 29, 2002
Jon M. Huppenthal, Colorado Springs, CO (US);
Thomas R. Seeman, Colorado Springs, CO (US);
Lee A. Burton, Divide, CO (US);
Jon M. Huppenthal, Colorado Springs, CO (US);
Thomas R. Seeman, Colorado Springs, CO (US);
Lee A. Burton, Divide, CO (US);
SRC Computers, Inc., Colorado Springs, CO (US);
Abstract
A computer system architecture and memory controller for close-coupling within a hybrid computing system using an adaptive processor interface port ('APIP') added to, or in conjunction with, the memory and I/O controller chip of the core logic. Memory accesses to and from this port, as well as the main microprocessor bus, are then arbitrated by the memory control circuitry forming a portion of the controller chip. In this fashion, both the microprocessors and the adaptive processors of the hybrid computing system exhibit equal memory bandwidth and latency. In addition, because it is a separate electrical port from the microprocessor bus, the APIP is not required to comply with, and participate in, all FSB protocol. This results in reduced protocol overhead which results higher yielded payload on the interface.