The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2006
Filed:
Feb. 10, 2003
Applicants:
Deepak Sabharwal, New Delhi, IN;
Izak Kense, Fremont, CA (US);
Alexander Shubat, Fremont, CA (US);
Inventors:
Assignee:
Virage Logic Corporation, Fremont, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 17/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
Methods and apparatuses in which a ROM memory array has virtual-grounded source lines programmed in layer physically higher than the diffusion layer. The ROM memory array may include a diffusion layer, one or more virtual-grounded source lines, and one or more bit lines. At least one of the virtual-grounded source lines is programmed with a layer physically higher than the diffusion layer.