The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2006

Filed:

Nov. 13, 2002
Applicants:

Kenneth C. Adkins, Fremont, CA (US);

Theodore Martin Myers, Los Altos, CA (US);

John Tabler, San Jose, CA (US);

Anurag Kaplish, Mountain View, CA (US);

Thomas J. O'obrien, Campbell, CA (US);

Inventors:

Kenneth C. Adkins, Fremont, CA (US);

Theodore Martin Myers, Los Altos, CA (US);

John Tabler, San Jose, CA (US);

Anurag Kaplish, Mountain View, CA (US);

Thomas J. O'Obrien, Campbell, CA (US);

Assignee:

Summit Microelectronics, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 3/16 (2006.01);
U.S. Cl.
CPC ...
Abstract

A control loop system is provided that employs an active DC output control circuit that more accurately calibrates the desire voltage at a load, e.g. 3.3 volts, by adjusting a trim pin on a DC/DC converter. In a first embodiment, an active DC output control circuit calibrates a DC/DC converter that is connected to a single load. In a second embodiment, an active DC output control circuit calibrates multiple DC/DC converters that are connected to multiple loads.


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