The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2006
Filed:
Nov. 12, 2002
Thomas P. Duffy, Chandler, AZ (US);
John Ryan Goodfellow, Mesa, AZ (US);
Robert T. Carroll, Andover, MA (US);
Kevin J. Cote, Ocotillo, AZ (US);
Sampath K. V. Karikalan, Phoenix, AZ (US);
Suresh Golwalkar, Phoenix, AZ (US);
Thomas P. Duffy, Chandler, AZ (US);
John Ryan Goodfellow, Mesa, AZ (US);
Robert T. Carroll, Andover, MA (US);
Kevin J. Cote, Ocotillo, AZ (US);
Sampath K. V. Karikalan, Phoenix, AZ (US);
Suresh Golwalkar, Phoenix, AZ (US);
Primarion, Inc., Phoenix, AZ (US);
Abstract
A semiconductor device package is disclosed which includes inter-digitated input and output bond wires configured to increase the negative mutual inductive coupling between the wires, thus reducing the overall parasitic inductance of the device. In one embodiment, the microelectronic component includes a semiconductor device coupled to a substrate, such as a lead frame, a first set of bond wires connected to the semiconductor device for providing current flow into the semiconductor device, and a second set of bond wires that are in a current loop with the first set of bond wires and are connected to the semiconductor device for providing current flow out of the semiconductor device, wherein the first and second set of bond wires are configured in an inter-digitated pattern to increase the magnitude of mutual inductive coupling between the first and second set of bond wires. In one embodiment, the semiconductor device comprises a single semiconductor chip and the lead frame comprises a Quad Flat No-Lead (QFN) lead frame. Other embodiments include multiple chips and/or multiple lead frames.