The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2006

Filed:

Dec. 03, 2002
Applicants:

Kenji Fukunabe, Sagamihara, JP;

Masanobu Okada, Sagamihara, JP;

Kazuyoshi Nakaya, Yokohama, JP;

Inventors:

Kenji Fukunabe, Sagamihara, JP;

Masanobu Okada, Sagamihara, JP;

Kazuyoshi Nakaya, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01R 9/00 (2006.01); H05K 3/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a circuit board, when lands provided on a rear surface of a substrate are each separated into a mainland and a sub-land, warping or other defects of the substrate can be ignored when soldering, and the substrate can be mounted with a high bonding strength. On the rear surface of a module substrate, partitions are each provided to separate a metal film into the mainland and the sub-land. Accordingly, when the substrate is mounted on a motherboard, solder applied beforehand from each end-surface electrode to the mainland can be largely protruded downward from the mainland, and warping or other defects of the substrate can be ignored by this protruding portion of the solder. In addition, in the state in which the substrate is mounted, since the solder is pushed out from between the mainland and the motherboard and overflows the partition, both the mainland and the sub-land can be soldered to the motherboard side, and hence stable bonding can be obtained at a large bonding area.


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