The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2006
Filed:
Nov. 19, 2003
Joseph A. Iadanza, Hinesburg, VT (US);
Raminderpal Singh, Essex Junction, VT (US);
Sebastian T. Ventrone, South Burlington, VT (US);
Ivan L. Wemple, Shelburne, VT (US);
Joseph A. Iadanza, Hinesburg, VT (US);
Raminderpal Singh, Essex Junction, VT (US);
Sebastian T. Ventrone, South Burlington, VT (US);
Ivan L. Wemple, Shelburne, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for designing an integrated circuit having multiple voltage domains, including: (a) generating a logical integrated circuit design from information contained in a high-level design file, the high-level design file defining global connection declarations and voltage domain connection declarations; (b) synthesizing the logical integrated circuit design into a synthesized integrated circuit design based upon the logical integrated circuit design, information in a preferred components file and information in a voltage domain definition file; (c) generating a noise model from the synthesized integrated circuit design based on information in the voltage domain definition file and a design constraint file; and (d) simulating the noise model against constraints in the design constraint file and constraints in a circuit level profile file to determine if the synthesized integrated circuit design meets predetermined noise simulation targets.