The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2006
Filed:
Apr. 08, 2004
Prakash Gothoskar, Allentown, PA (US);
Margaret Ghiron, Allentown, PA (US);
Vipulkumar Patel, Monmouth Junction, NJ (US);
Robert Keith Montgomery, Easton, PA (US);
Kalpendu Shastri, Orefield, PA (US);
Soham Pathak, Allentown, PA (US);
Katherine A. Yanushefski, Zionsville, PA (US);
Prakash Gothoskar, Allentown, PA (US);
Margaret Ghiron, Allentown, PA (US);
Vipulkumar Patel, Monmouth Junction, NJ (US);
Robert Keith Montgomery, Easton, PA (US);
Kalpendu Shastri, Orefield, PA (US);
Soham Pathak, Allentown, PA (US);
Katherine A. Yanushefski, Zionsville, PA (US);
SiOptical, Inc., Allentown, PA (US);
Abstract
A system and method for providing the layout of non-Manhattan shaped integrated circuit elements using a Manhattan layout system utilizes a plurality of minimal sized polygons (e.g., rectangles) to fit within the boundaries of the non-Manhattan element. The rectangles are fit such that at least one vertex of each rectangle coincides with a grid point on the Manhattan layout system. Preferably, the rectangles are defined by using the spacing being adjacent grid points as the height of each rectangle. As the distance between adjacent grid points decreases, the layout better matches the actual shape of the non-Manhattan element. The system and method then allows for electrical and optical circuit elements to be laid out simultaneously, using the same layout software and equipment.