The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2006

Filed:

Feb. 27, 2004
Applicants:

Joerg Vollrath, Olching, DE;

Stephan Schröder, München, DE;

Tobias Hartner, Hamburg, DE;

Inventors:

Joerg Vollrath, Olching, DE;

Stephan Schröder, München, DE;

Tobias Hartner, Hamburg, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated semiconductor circuit includes a cell array having memory cells which can be read by word lines and bit lines. Two bit lines in each case are connected to inputs of the same signal amplifier. In order to compensate for parasitic capacitances which arise at thin sidewall insulations between the patterned word lines and adjacent bit line contacts which connect the bit lines located at a higher level to the active regions located at a deeper level, two additional word lines and dummy contacts of the bit lines are dummy contacts lead past this additional word lines. The additional parasitic capacitances produced by the dummy contacts alter the electrical potential of the respective reference bit line at the signal amplifier in the same way as the parasitic capacitances of activated bit lines, as a result of which the measured differential potential is corrected with respect to the parasitic effects.


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