The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2006

Filed:

Feb. 24, 2004
Applicants:

In-wook Cho, Yongin-si, KR;

Nae-in Lee, Seoul, KR;

Kwang-wook Koh, Sungnam-si, KR;

Geum-jong Bae, Suwon-si, KR;

Sang-su Kim, Suwon-si, KR;

Jin-hee Kim, Sungnam-si, KR;

Sung-ho Kim, Gyeonggi-do, KR;

Ki-chul Kim, Suwon-si, KR;

Inventors:

In-Wook Cho, Yongin-si, KR;

Nae-In Lee, Seoul, KR;

Kwang-Wook Koh, Sungnam-si, KR;

Geum-Jong Bae, Suwon-si, KR;

Sang-Su Kim, Suwon-si, KR;

Jin-Hee Kim, Sungnam-si, KR;

Sung-Ho Kim, Gyeonggi-do, KR;

Ki-Chul Kim, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a non-volatile semiconductor memory device begins by forming a dielectric layer pattern having an ONO composition on a substrate. A polysilicon layer is formed on the substrate including over the dielectric layer pattern. The polysilicon layer is patterned to form a split polysilicon layer pattern that exposes part of the dielectric layer pattern. The exposed dielectric layer is etched, and then impurities are implanted into portions of the substrate using the split polysilicon layer pattern as a mask to thereby form a source region having a vertical profile in the substrate.


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