The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2006
Filed:
Sep. 12, 2002
Karthik Ramaswamy, Sunnyvalle, CA (US);
Kent Dickey, Westford, MA (US);
Karthik Ramaswamy, Sunnyvalle, CA (US);
Kent Dickey, Westford, MA (US);
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Abstract
In a technique for testing processor interrupt logic, interrupts are sent to a microprocessor under test in a random order to test the processor interrupt logic of the microprocessor under test. The processor interrupt logic is considered to have failed the test if the microprocessor under test services a new interrupt having a priority level equal to or lower than a priority level of a previously received interrupt being serviced just prior to the receipt of the new interrupt. Furthermore, pseudo-masked interrupts are included in the interrupts being sent to the microprocessor under test. If a pseudo-masked interrupt is serviced by the microprocessor under test, the processor interrupt logic is considered to have failed the test. On the other hand, if the pseudo-masked interrupt is not serviced by the microprocessor under test, a lower (that is, soft) limit of the pseudo-masked interrupts is increased to that of the received pseudo-masked interrupt which has not been serviced by the microprocessor under test.