The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2006

Filed:

Nov. 28, 2001
Applicants:

Hayden Clavie Cranford, Jr., Apex, NC (US);

Stacy Jean Garvin, Curhan, NC (US);

Vernon Roberts Norman, Cary, NC (US);

Paul Alan Owczarski, Raleigh, NC (US);

Martin Leo Schmatz, Gallen, CH;

Joseph Marsh Stevens, Morrisville, NC (US);

Inventors:

Hayden Clavie Cranford, Jr., Apex, NC (US);

Stacy Jean Garvin, Curhan, NC (US);

Vernon Roberts Norman, Cary, NC (US);

Paul Alan Owczarski, Raleigh, NC (US);

Martin Leo Schmatz, Gallen, CH;

Joseph Marsh Stevens, Morrisville, NC (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03D 3/24 (2006.01);
U.S. Cl.
CPC ...
Abstract

A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver. The system comprises a phase locked loop (PLL) control circuit, a phase rotator circuit, a phase buffer circuit, and an equalization driver circuit. The phase rotator circuit is configured to acquire a clock phase from the phase locked loop control circuit and modulo shift the clock phase into a desired phase angle. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop, a multi-stage voltage controlled oscillator, a voltage comparator, a PLL control logic, a digital to analog counter and a low pass filter. The fine loop includes the oscillator, a frequency divider, a phase-frequency detector, a charge pump and a loop filter.


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