Method and circuit for controlling generation of column selection line signal

Abstract

There are provided a method and circuit for controlling generation of a column selection line signal. The method includes determining whether a current mode is a normal operation mode or a test operation mode; receiving an activated test operation mode signal and an activated first clock signal and outputting a column selection line signal with an activation time proportional to an activation time of the first clock signal, when the current mode is the test operation mode; and outputting the column selection line signal that is activated in response to the activated first clock signal and is deactivated in response to an activated second clock signal, when the current mode is the normal operation mode. An activation time of the first clock signal is proportional to that of an external clock signal. In the test operation mode, a command is performed during one period of the external clock signal. A column selection line signal can be generated without an increase in circuit logic, depending on a type of operation mode. Accordingly, it is possible to effectively realize CCD=1tCK in a semiconductor memory device, which operates in the DDRmode, in a test operation mode.