The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2006
Filed:
Oct. 28, 2003
Philip Y. Pan, Fremont, CA (US);
Chiakang Sung, Milpitas, CA (US);
Joseph Huang, San Jose, CA (US);
Bonnie Wang, Cupertino, CA (US);
Khai Nguyen, San Jose, CA (US);
Xiaobao Wang, Santa Clara, CA (US);
Gopinath Rangan, Santa Clara, CA (US);
IN Whan Kim, San Jose, CA (US);
Yan Chong, Stanford, CA (US);
Philip Y. Pan, Fremont, CA (US);
Chiakang Sung, Milpitas, CA (US);
Joseph Huang, San Jose, CA (US);
Bonnie Wang, Cupertino, CA (US);
Khai Nguyen, San Jose, CA (US);
Xiaobao Wang, Santa Clara, CA (US);
Gopinath Rangan, Santa Clara, CA (US);
In Whan Kim, San Jose, CA (US);
Yan Chong, Stanford, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Methods and apparatus for a dual-port SRAM in a programmable logic device. One embodiment provides a programmable logic integrated circuit including a dual-port memory. The memory includes a plurality of memory storage cells, and each memory storage cell has a memory cell having a first node and a second node, a first series of devices connected between a first data line and the first node of the memory cell, and a second series of devices connected between a second data line and the second node of the memory cell. A read cell is connected to the second node of the memory cell. A word line is connected to a first device in the first series of devices, a second device in the second series of devices, and the read cell.