The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2006
Filed:
Feb. 25, 2003
Toyoki Suzuki, Kasugai, JP;
Toyoki Suzuki, Kasugai, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
There is provided an output buffer circuit which can realize high speed voltage transition of an output signal while generation of noise due to signal transition is suppressed. On the occasion of driving a PMOS transistor P, in the period of the state I, when the NMOS transistor Nand NMOS transistors N, Nare turned ON, voltage of the output stage PMOS gate terminal APis sharply dropped and the PMOS transistor Pis turned ON. While the signal is propagated in the shortest delay time to the circuit of next stage, when the NMOS transistor Nand NMOS transistor Nare turned ON in the state II, disturbance of signal waveform can be suppressed by limiting a through-rate of the voltage drop of the output stage PMOS gate terminal AP. Driving capability of the PMOS transistor Pcan be variably controlled by controlling the bias condition of a control signal APby switching, for every state, the NMOS transistors Nto Nwhich are turned ON.