The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2006
Filed:
Mar. 12, 2003
Applicant:
Masaharu Mizuno, Kanagawa, JP;
Inventor:
Masaharu Mizuno, Kanagawa, JP;
Assignee:
NEC Electronics Corporation, Kanagawa, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H30K 19/177 (2006.01);
U.S. Cl.
CPC ...
Abstract
A general-purpose logic cell array includes a plurality of cells and a lower wiring layer. The plurality of cells are formed on a substrate, and each of the plurality of cells includes a plurality of transistors. The lower wiring layer is formed above the plurality of cells, and which connects the plurality of transistors in each of the plurality of cells such that each of the plurality of cells has an elementary logic circuit. Information of the general-purpose logic cell array is provided to a user. The elementary logic circuits may be one of a gate circuit, a selector, an inverter and a flip-flop.