The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2006
Filed:
Sep. 04, 2003
George J. Kluth, Campbell, CA (US);
Robert B. Clark-phelps, San Jose, CA (US);
Joong S. Jeon, Cupertino, CA (US);
Huicai Zhong, Wappinger Falls, NY (US);
Arvind Halliyal, Cupertino, CA (US);
Mark T. Ramsbey, Sunnyvale, CA (US);
Robert B. Ogle, Jr., San Jose, CA (US);
Kuo T. Chang, Saratoga, CA (US);
Wenmei LI, Sunnyvale, CA (US);
George J. Kluth, Campbell, CA (US);
Robert B. Clark-Phelps, San Jose, CA (US);
Joong S. Jeon, Cupertino, CA (US);
Huicai Zhong, Wappinger Falls, NY (US);
Arvind Halliyal, Cupertino, CA (US);
Mark T. Ramsbey, Sunnyvale, CA (US);
Robert B. Ogle, Jr., San Jose, CA (US);
Kuo T. Chang, Saratoga, CA (US);
Wenmei Li, Sunnyvale, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
According to one embodiment, a memory cell structure comprises a semiconductor substrate, a first silicon oxide layer situated over the semiconductor substrate, a charge storing layer situated over the first silicon oxide layer, a second silicon oxide layer situated over the charge storing layer, and a gate layer situated over the second silicon oxide layer. In the exemplary embodiment, the charge storing layer comprises silicon nitride having reduced hydrogen content, e.g., in the range of about 0 to 0.5 atomic percent. As a result, the reduced hydrogen content reduces the charge loss in the charge storing layer. The reduced charge loss in the charge storing layer has the benefit of reducing threshold voltage shifts, programming data loss, and programming capability loss in the memory device, thereby improving memory device performance.