The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2006
Filed:
Sep. 03, 2003
Soon-sung Yoo, Kyoungsangbuk-do, KR;
Dong-yeung Kwak, Taegu, KR;
Hu-sung Kim, Seoul, KR;
Yu-ho Jung, Kyoungsangbuk-do, KR;
Yong-wan Kim, Kyoungsangbuk-do, KR;
Duk-jin Park, Taegu, KR;
Woo-chae Lee, Kyoungsangbuk-do, KR;
Soon-Sung Yoo, Kyoungsangbuk-do, KR;
Dong-Yeung Kwak, Taegu, KR;
Hu-Sung Kim, Seoul, KR;
Yu-Ho Jung, Kyoungsangbuk-do, KR;
Yong-Wan Kim, Kyoungsangbuk-do, KR;
Duk-Jin Park, Taegu, KR;
Woo-Chae Lee, Kyoungsangbuk-do, KR;
LG.Philips LCD Co., Ltd., Seoul, KR;
Abstract
A TFT array substrate has a PAI pattern, and the PAI pattern has an over-etched portion of the pure amorphous silicon layer. This over-etched portion prevents a short between the pixel electrode and the pure amorphous silicon layer (i.e., the active layer). The over-etched portion also enables the aperture ratio to increase a gate line over a said substrate; a data line over the said substrate being perpendicular to the gate line; a passivation layer covering the data line, the passivation layer divided into a residual passivation layer and a etched passivation layer; a doped amorphous silicon layer formed under the data line and corresponding in size to the data line; a pure amorphous silicon layer formed under the doped amorphous silicon layer and having a over-etched portion in the peripheral portions, wherein the over-etched portion is over-etched from the edges of the residual passivation layer toward the inner side; an insulator layer under the pure amorphous silicon layer; a TFT formed near the crossing of the gate line and the data line; and a pixel electrode overlapping the data line and contacting the TFT.