The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2006

Filed:

Mar. 11, 2004
Applicants:

Taiji Ema, Kawasaki, JP;

Tohru Anezaki, Kawasaki, JP;

Inventors:

Taiji Ema, Kawasaki, JP;

Tohru Anezaki, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/119 (2006.01);
U.S. Cl.
CPC ...
Abstract

The semiconductor storage device comprises memory cell transistors formed on a semiconductor substrate; first insulation filmscovering the top surfaces and the side surfaces of gate electrodesof the memory cell transistors; through-holesopened on first diffused layers; a second insulation filmwith through-holesopened on first diffused layersand through-holesopened on second diffused layersformed in; capacitors formed on the inside walls and the bottoms of the through-holesand including capacitor storage electrodes, connected to the first diffused layers; capacitor dielectric filmscovering the capacitor storage electrodes, and capacitor-opposed electrodescovering at least a part of the capacitor dielectric films; and, contact conducting filmsformed on the inside walls and bottoms of the through-holes, and connected to the second diffused layers. This structure of the semiconductor storage device makes it unnecessary to secure an alignment allowance for alignment of the through-holesopened on the first diffused layerand the through-holesopened on the second diffused layerwith the gate electrode, which permits the semiconductor storage device to have a small memory cell area.


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