Method of manufacturing a semiconductor non-volatile memory

Abstract

A method of manufacturing a semiconductor device comprising a non-volatile memory with memory transistors and selection transistors. In this method a semiconductor body is provided with strip-shaped active regions () which are mutually isolated by field-oxide regions (of). On the surface () a first system of conductorsis then formed which are directed perpendicularly to the active regions and are covered by an insulating layer (), charge storage regions () being formed below these conductors, at the location where these conductors and the active regions cross each other. These conductors form word lines of the memory and, at the location where said conductors and the active regions cross each other, they form control gates. Next, a conductive layer () is deposited and planarized. The planarized conductive layer () is then provided with an etch mask with strips directed perpendicularly to the active regions, which strips extend above and next to the conductors (). Then a second system of conductors () is etched in the planarized conductive layer. The planarized layer here covers the conductors () with the insulating top layer () completely, so that the conductors () of the second system extend above the conductors () of the first system. Thus a very compact memory can be produced, enabling data written in the memory to be read out in very short times.